(China (Mainland))
Product Summary
The SI3552DV-T1-E3 is a typical electrical characteristics of the n- and p-channel vertical DMOS. The SI3552DV-T1-E3 is extracted and optimized over the -55 to 125℃ temperature ranges under the pulsed 0-V to 5-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device.
Parametrics
Absolute maximum ratings:(1)Gate Threshold Voltage, VGS(th), VDS = V, VGS, ID = 250μA, N-Ch: 1.9V; (2)Gate Threshold Voltage, VGS(th), VDS = V, VGS, ID = -250μA, P-Ch: 2.13V; (3)On-State Drain Current, ID(on), VDS = 5V, VGS = 10V, N-Ch: 51A; (4)On-State Drain Current, ID(on), VDS = -5V, VGS = -10V, P-Ch: 24A; (5)Drain-Source On-State Resistance, rDS(on), VGS = 10V, ID = 2.5A, N-Ch: 0.09Ω; (6)Drain-Source On-State Resistance, rDS(on), VGS = -10V, ID = -1.8A, P-Ch: 0.177Ω; (7)Drain-Source On-State Resistance, rDS(on), VGS = 4.5V, ID = 2.0A, N-Ch: 0.134Ω; (8)Drain-Source On-State Resistance, rDS(on), VGS = -4.5V, ID = -1.2A, P-Ch: 0.134Ω; (9)Forward Transconductance, gfs, VDS = 10V, ID = 2.5A, N-Ch: 4.3S; (10)Forward Transconductance, gfs, VDS = -15V, ID = -1.2A, P-Ch: 2.5S; (11)Diode Forward Voltage, VSD, IS = 1.05 A, VGS = 0V, N-Ch: 0.81V; (12)Diode Forward Voltage, VSD, IS = -1.05 A, VGS = 0V, P-Ch: -0.81V.
Features
Features:(1)N- and P-Channel Vertical DMOS; (2)Macro Model (Subcircuit Model); (3)Level 3 MOS; (4)Apply for both Linear and Switching Application; (5)Accurate over the -55 to 125℃ Temperature Range; (6)Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics.
Diagrams
| Image | Part No | Mfg | Description |  |
Pricing (USD) |
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 SI3552DV-T1-E3 |
Vishay/Siliconix |
MOSFET 30V 2.5/1.8A |
Data Sheet |
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