SAB80C166MT3DA

Product Summary

The SAB80C166MT3DA is the first representative of the Siemens SAB80C166MT3DA family of full featured single-chip CMOS microcontrollers. It combines high CPU performance (up to 10 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. The memory space of the SAB80C166MT3DA is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 256 KBytes.

Parametrics

Absolute maximum ratings:(1)Input low voltage, VIL SR: –0.5 to 0.2VCC–0.1V; (2)Input high voltage RSTIN, VIH1 SR: 0.6 VCC VCC + 0.5V; (3)Input high voltage XTAL1, VIH2 SR: 0.7 VCC VCC + 0.5V; (4)Output low voltage (Port 0, Port 1, Port 4, ALE, RD,WR, BHE, CLKOUT, RSTOUT), VOL CC: 0.45V; (5)Output low voltage (all other outputs), VOL1 CC: 0.45V; (6)RSTIN pullup resistor, RRST CC: 50 to 150kW; (7)Read inactive current, IRH: -40mA; (8)Read active current, IRL: -500mA; (9)ALE inactive current, IALEL: –150mA; (10)ALE active current, IALEH, 2100mA; (11)XTAL1 input current, IIL CC: ±20 mA; (12)Power supply current, ICC: – 50+5 * fCPUmA; (13)Idle mode supply current, IID: – 30 +1.5 * fCPU mA; (14)Power-down mode supply current, IPD; – 50mA.

Features

Features: (1)High Performance 16-bit CPU with 4-Stage Pipeline; (2)100 ns Instruction Cycle Time at 20 MHz CPU Clock; (3)500 ns Multiplication (16 ′ 16 bit), 1 ms Division (32 / 16 bit); (4)Enhanced Boolean Bit Manipulation Facilities; (5)Register-Based Design with Multiple Variable Register Banks; (6)Single-Cycle Context Switching Support; (7)Up to 256 KBytes Linear Address Space for Code and Data; (8)1 KByte On-Chip RAM; (9)32 KBytes On-Chip ROM (SAB 83C166 only); (10)Programmable ExternaBus Characteristics for Different Address Ranges; (11)8-Bit or 16-Bit ExternaData Bus; (12)Multiplexed or Demultiplexed ExternaAddress/Data Buses; (13)Hold and Hold-Acknowledge Bus Arbitration Support; (14)512 Bytes On-Chip SpeciaFunction Register Area; (15)Idle and Power Down Modes; (16)8-ChanneInterrupt-Driven Single-Cycle Data Transfer Facilities via PeripheraEvent; (17)Controller (PEC); (18)16-Priority-LeveInterrupt System; (19)10-Channe10-bit A/D Converter with 9.7 ms Conversion Time; (20)16-hanneCapture/Compare Unit; (21)Two Multi-FunctionaGeneraPurpose Timer Units with 5 Timers; (22)Two SeriaChannels (USARTs); (23)Programmable Watchdog Timer; (24)Up to 76 GeneraPurpose I/O Lines; (25)Supported by a Wealth of Development Tools like C-Compilers, Macro-Assembler Packages,; (26)Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers,; (27)Programming Boards; (28)On-Chip Bootstrap Loader; (29)100-Pin Plastic MQFP Package (EIAJ).

Diagrams