(China (Mainland))
Product Summary
The CD4011BE is a kind of CD4011B which provides the system designer with direct implementation of the HAND function and supplement the existing family of CMOS gates. The CD4011BE is supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PWR suffix). All inputs and outputs are buffered. The CD4011B and CD4011BE types also are supplied in 14-lead thin shrink small-outline packages (PW suffix).
Parametrics
Absolute maximum ratings:(1)DC supply-voltage range, (VDD) voltages referenced to VSS terminal): -0.5V to +20V; (2)input voltage range, all inputs: -0.5V to VDD + 0.5V; (3)DC input current, any one input: 士10mA; (4)power dissipation per package (PD): For TA = -55°C to +100°C: 500m W; for TA+100°C to +125°C: derate linearly at 12W/°C to 200mW; (5)device dissipation pea output transistor; (6)for TA=full package-temperature range (all package tyres): 100mW; (7)operating-temperature range (TA): -55°C to 125°C; (8)storage temperature range (Tstg): -65°C to +150°C.
Features
Features: (1)propagation delay time=60ns (typ) at CL=50 pF, Vdd=10V; (2)buffered input and outputs; (3)standardized symmetrical output characteristics; (4)Maximum input current of 1 μA at 18 V over full package temperature range; 100 nA at 18 V and 25°C; (5)100% tested for quiescent current at 20 V; (6)5-V, 70-V, and 15-V parametric ratings; (7)noise margin lover full package temperature range: 1 V at VDD=5V 2V at VDD=0 V 2.5 V at VDD=15V; (8)meets all requirements of JEDEC Tentative Standard No.13B "standard specificatiuns for description of "B" Series CMOS devices".
Diagrams
| Image | Part No | Mfg | Description |  |
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 CD4011BE |
Texas Instruments |
Gates (AND / NAND / OR / NOR) Quad 2-Input |
Data Sheet |
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CD4011BEE4 |
Texas Instruments |
Gates (AND / NAND / OR / NOR) Quad 2-Input |
Data Sheet |
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